This invention relates to methods of manufacturing an electronic device (for example a liquid crystal display with an integrated drive circuit) having thin-film circuit elements and tracks on an insulating substrate, and relates particularly to the provision of means for protecting against problems due to charging of the thin-film tracks during an ion implantation step in the manufacture of the device. The invention also relates to the electronic devices as manufactured by such a method.
Nowadays thin-film circuit technologies are being used for manufacture of liquid crystal display (LCD) devices and many other large area electronic devices, for example ROMs (read only memories) and other data stores, and various image sensors. Such devices have an insulating substrate (for example of an inexpensive glass or plastics material) on which a pattern of thin-film circuit elements are formed by steps which include depositing films of various materials (for example insulators, semiconductors, semi-insulators, metals) on the substrate and etching the films into a desired pattern. Conductive tracks and various active circuit elements, for example thin-film polycrystalline silicon transistors, may be formed in this way. Some manufacturing methods also involve one or more steps of implanting ions in areas of at least one of the films to modify the conductivity properties of the film, for example to dope a source or drain or gate region of such a transistor. In the LCD or other devices mentioned above, the circuit elements may be arranged to form, for example, a matrix of switching elements and one or more drive circuits for driving the matrix.
Such a method is known from published Japanese patent application Kokai JP-A-60-251665, as disclosed in the English language Patents Abstracts of Japan published by the Japanese Patent Office and in the drawings of JP-A-60-251665, the whole contents of which are hereby incorporated herein as reference material. A group of thin-film parallel tracks forms part of the pattern of circuit elements, and these are provided on the substrate before an ion implantation step. Also provided as a part of the thin-film pattern on the substrate before the implantation step is a discharge path which extends from within the group of tracks, outwards towards a periphery of the substrate. The discharge path serves to mitigate charging of the tracks during the ion implantation, and the particular problem mentioned in JP-A-60-251665 is to prevent dielectric breakdown of the gate insulating film of the thin-film transistors.
JP-A-60-251665 discloses forming the discharge path and the group of tracks as a single continuous conductor pattern from the same thin film, which interconnects and so short-circuits the tracks. These tracks provide the gate lines for transistors of the device. After the ion implantation step the gate lines are isolated from each other by etching away areas of these interconnections which form the discharge path. The areas to be etched away are defined by a mask which needs to be aligned with respect to the spaces between the parallel gate tracks. This subsequent mask-alignment requirement necessitates the location of the discharge path of JP-A-60-251665 at an area where there is a comparatively wide spacing between the neighbouring tracks, if the gate tracks themselves are not to be etched into at their edges, and if the yield of good devices from a manufacturing process is not to be reduced.
The present applicant finds that it is sometimes desirable to provide a discharge path at a location where tracks are more closely spaced and where the spacing is insufficient to permit a subsequent mask-alignment and etching step to be carried out without causing a significant reduction in yield. The present applicant also finds that, with large area substrates (for example about 100 cm.sup.2 and more) and due to the insulating nature of an underlying film and/or of the substrate itself, the charging problem during ion implantation may be such that, instead of or as well as dielectric breakdown in an active circuit element (for example, the gate insulator of a thin-film transistor), parts of the thin-film pattern (and in particular parallel tracks over part of their length) are blown away by the resulting severe discharges. Such discharges and the resulting track damage can be particularly severe in the vicinity of large exposed areas of the insulating film and/or substrate. For this reason, the present applicant finds that it is desirable in the manufacture of many devices to provide implantation discharge paths at other locations than adjacent to the active circuit elements, and for example to provide such discharge paths from various locations along the length of closely spaced parallel tracks.